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74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
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HIGH SPEED: fMAX = 160 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 A (MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHCT74AMTR 74VHCT74ATTR
DESCRIPTION The 74VHCT74A is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse.
CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
December 2004
Rev. 3
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Figure 2: Input Equivalent Circuit Table 2: Pin Description
PIN N 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage
4, 10 5, 9 6, 8 7 14
1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC
Table 3: Truth Table
INPUTS CLR L H L H H H
X : Don't Care
OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET
PR H L L H H H
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
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Table 4: Absolute Maximum Ratings
Symbol VCC VI VO VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) VCC = 0V 2) High or Low State
Table 5: Recommended Operating Conditions
Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 5.0 0.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V V C ns/V
1) VCC = 0V 2) High or Low State 3) VIN from 0.8V to 2V
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Table 6: DC Specifications
Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 0 IO=-50 A IO=-8 mA IO=50 A IO=8 mA VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V TA = 25C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 0.1 2 1.35 0.5 4.5 4.4 3.8 0.1 0.44 1.0 20 1.5 5.0 Typ. Max. Value -40 to 85C Min. 2 0.8 4.4 3.7 0.1 0.55 1.0 20 1.5 5.0 Max. -55 to 125C Min. 2 0.8 Max. V V V V A A mA A Unit
VIH VIL VOH VOL II ICC +ICC
High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current
IOPD
Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0
(*)
Value TA = 25C Min. Typ. 5.8 6.3 7.6 8.1 Max. 7.8 8.8 10.4 11.4 5.0 5.0 5.0 0.0 3.5 -40 to 85C Min. 1.0 1.0 1.0 1.0 Max. 9.0 10.0 12.0 13.0 5.0 5.0 5.0 0.0 3.5 80 65 80 65 -55 to 125C Min. 1.0 1.0 1.0 1.0 Max. 9.0 10.0 12.0 13.0 5.0 5.0 5.0 0.0 3.5 ns ns ns ns ns ns MHz ns Unit
CL (pF) 15 50 15 50
tPLH tPHL tPLH tPHL tW tW ts th tREM fMAX
Propagation Delay Time CK to Q or Q Propagation Delay Time PR or CLR to Q or Q CK Pulse Width HIGH or LOW PR or CLR Pulse Width LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Removal Time PR or CLR to CK Maximum Clock Frequency
5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0
(*)
15 50
100 80
160 140
(*) Voltage range is 5.0V 0.5V
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Table 8: Capacitive Characteristics
Test Condition Symbol Parameter TA = 25C Min. CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) Typ. 6 21 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate)
Figure 4: Test Circuit
CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
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Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
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Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Removal Times (f=1MHz; 50% duty cycle)
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Figure 8: Waveform - Pulse Width
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SO-14 MECHANICAL DATA
DIM. A A1 A2 B C D E e H h L k ddd 5.8 0.25 0.4 0 mm. MIN. 1.35 0.1 1.10 0.33 0.19 8.55 3.8 1.27 6.2 0.50 1.27 8 0.100 0.228 0.010 0.016 0 TYP MAX. 1.75 0.25 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.244 0.020 0.050 8 0.004 inch TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.344 0.157
0016019D
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TSSOP14 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
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Tape & Reel SO-14 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.4 9 2.1 3.9 7.9 12.8 20.2 60 22.4 6.6 9.2 2.3 4.1 8.1 0.252 0.354 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.260 0.362 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
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Tape & Reel TSSOP14 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
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Table 9: Revision History
Date 16-Dec-2004 Revision 3 Description of Changes Order Codes Revision - pag. 1.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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